1. Field of the Invention
The present invention relates to a liquid crystal displaying apparatus in which an image having no flicker is displayed and a display characteristic in gray scale is excellent.
2. Description of the Related Art
2.1. First Previously Proposed Art
FIG. 1 is a block diagram of a conventional matrix type liquid crystal displaying apparatus, and FIG. 2 is a circuit view of a pixel element arranged in an image displaying unit of the conventional matrix type liquid crystal displaying apparatus. The pixel element of FIG. 2 is disclosed in a patent gazette No. H3-34077 (1991) (corresponding to U.S. Pat. No. 4,532,506) as an invention of Kitazima and Kawakami.
As shown in FIG. 1, a conventional matrix type liquid crystal displaying apparatus 31 is composed of an X directional shift register 33 for outputting a plurality of pixel signals CP one after another in an X direction every one horizontal scanning period (or 1 H time-period), a Y directional shift register 35 for outputting a plurality of 1 H scanning time signals one after another in a Y direction every one frame period, a first buffer 34 for outputting a plurality of picture signals corresponding to the pixel signals CP output from the X directional shift register 33 one after another, a second buffer 35 for outputting a plurality of scanning signals corresponding to the 1 H scanning time signals output from the Y directional shift register 35 one after another, an image displaying unit 32 for displaying an image according to the picture signals transmitted from the first buffers 34 through a plurality of source signal lines 11 and the scanning signals transmitted from the second buffers 36 through a plurality of gate signal lines 12, and a voltage supplying circuit 37 for supplying a reference voltage to a plurality of pixel elements 30 of the image displaying unit 32.
In the above configuration, a plurality of pixel signals CP are output one after another from a plurality of first output terminals r.sub.1 to r.sub.n of the X directional shift register 33 arranged in series in the X direction, in synchronization with each horizontal scanning time signal (or clock pulse) D. Therefore, the pixel signals CP are output to the first buffer 34 every one horizontal scanning period (1 H time-period). Also, a plurality of frame time signals FST are output one after another from a plurality of second output terminals s.sub.1 to s.sub.n of the Y directional shift register 35 arranged in series in the Y direction as a plurality of 1 H scanning time signals, in synchronization with a plurality of line start signals (or a plurality of 1 H start signals) LST. Therefore, each of the 1 H scanning time signals corresponds to 1 H time-period (one horizontal scanning period), and the 1 H scanning time signals are output to the second buffer 36 every one frame period.
Thereafter, a plurality of voltages Vs1 to Vsn corresponding to the pixel signals CP output from the X directional shift register 33 are produced in the first buffer 34 and are output one after another to the pixel elements 30 of the image displaying unit 32 through the source signal lines 11a.sub.1 to 11a.sub.n as a plurality of picture signals. Also, a plurality of voltages Vg1 to Vgn corresponding to the 1 H scanning time signals output from the Y directional shift register 35 are produced in the second buffer 36 and are output one after another to the pixel elements 30 of the image displaying unit 32 through the gate signal lines 12a.sub.1 to 12a.sub.n as a plurality of scanning signals. Also, a reference voltage is supplied from the voltage supplying circuit 37 to the pixel elements 30 of the image displaying unit 32.
In the image displaying unit 32, the pixel elements 30a1, 30a2, . . . , 30an, . . . , 30n1, 30n2, . . . , 30nn are arranged in the X and Y directions in a matrix layout. For example, the pixel elements 30a1, 30a2, . . . , 30an are arranged on a first line extending in the X direction, and the pixel elements 30n1, 30n2, . . . , 30nn are arranged on a final line extending in the X direction.
As shown in FIG. 2, each of the pixel elements 30 is composed of a first MOS-FET (metal oxide semiconductor field effect transistor) 13 in which a gate G is connected with one gate signal line 12 and a drain D is connected with one source signal line 11, a second MOS-FET 14 in which a gate G is connected with a source S of the first MOS-PET 13 and a drain D is connected with the gate signal line 12, a condenser 15 for charging a voltage Vat to the gate G of the second MOS-FET 14 and discharging the voltage Vst to the earth, and a liquid crystal displaying device 16 for emitting light according to one scanning signal transmitted through the gate signal line 12.
In the above configuration, a piece of voltage information such as a voltage Vs1 or a zero voltage is maintained in the first MOS-FET 13 and the condenser 15 during one frame period for each pixel element 30. Also, a piece of pixel information is maintained in the second MOS-FET 14 and the liquid crystal displaying device 16 during one frame period for each pixel element 30, and the pixel information is displayed by the liquid crystal displaying device 16.
In detail, one voltage Vs of one picture signal corresponding to each of the pixel signals CP is supplied from the first buffer 34 to the drain D of one first MOS-FET 13 through one source signal line 11. Also, one voltage Vg1 of one scanning signal corresponding to each of the 1 H scanning time signals synchronized with one frame time signal FST is supplied from the second buffer 36 to the gate G of the first MOS-FET 13 through one gate signal line 12, and the first MOS-FET 13 is set to an "on" condition and is turned on. Therefore, the voltage Vs of the picture signal is charged to the condenser 15 through the drain D of the first MOS-FET 13 and the source S of the first MOS-FET 13, and a charging voltage Vst is applied to the gate of the second MOS-FET 14. Therefore, the second MOS-FET 14 is set to an "on" condition and is turned on. The charging voltage Vst is maintained by the condenser 15 until another voltage Vg1 corresponding to one scanning signal synchronized with one frame time signal FST is supplied to the gate G of the first MOS-FET 13 in a next frame.
Also, the voltage Vg1 of the scanning signal is applied to the drain D of the second MOS-FET 14 when the second MOS-FET 14 is set to the "on" condition, and the voltage Vg1 is applied to one electrode 16a of the liquid crystal displaying device 16 through the second MOS-FET 14. In this case, an alternating current exciting voltage is superimposed on the scanning signal, and a reference voltage is applied from the voltage supplying circuit 37 to a common electrode 16b of the liquid crystal displaying device 16. Therefore, the liquid crystal displaying device 16 is actuated according to the alternating current exciting voltage, and light is emitted from the liquid crystal displaying device 16.
Accordingly, because the liquid crystal displaying device 16 is actuated at the same frequency with that of the alternating current exciting voltage supplied from the outside, an image can be displayed in the pixel elements 30 of the image displaying unit 32 without any flicker. However, it is difficult to obtain an excellent display characteristic in gray scale. That is, it is difficult to distinguish a large number of gray degrees, ranging from a gray degree corresponding to a white to a gray degree corresponding to a black, from each other in an image.
2.2. Second Previously Proposed Art
Another conventional liquid crystal displaying apparatus in which an image is displayed in gray scale is known. However, in this liquid crystal displaying apparatus, because an actuating frequency for a liquid crystal displaying device is limited to a field frequency (60 Hz) or a frame frequency (30 Hz), so that there is a drawback that a flicker occurs in an image displayed by using the apparatus. Therefore, it is difficult that the conventional liquid crystal displaying apparatus obtains an excellent display characteristic in gray scale without any occurrence of a flicker.
As an example of the conventional liquid crystal displaying apparatus in which an image is displayed in gray scale, a matrix displaying apparatus disclosed in a patent gazette No. H3-34077 (1991) is described with reference to FIG. 3.
In this matrix displaying apparatus, the second MOS-FET 14 is omitted from each pixel element. That is, as shown in FIG. 3, each pixel element 41 in this matrix displaying apparatus is composed of a first MOS-FET 44 in which a gate G is connected with a gate signal line 43 and a drain D is connected with a source signal line 42, a condenser 45 of which one end is connected with a source S of the first MOS-FET 44, and a liquid displaying device 46 of which one electrode 46a is directly connected with the source S of the first MOS-FET 44.
In the above configuration, a piece of voltage information such as a voltage Vs or a zero voltage is maintained in the first MOS-FET 44 and the condenser 45 during one frame period for each pixel element 41. Thereafter, an actuating voltage Va relating to the maintained voltage Vs is applied to the electrode 46a of the liquid displaying device 46, and a piece of pixel information is displayed by the liquid crystal displaying device 46 during one frame period for each pixel element 41. In this case, the voltage Vs of a picture signal Sp applied to the drain D of the first MOS-FET 44 through the source signal line 42 is changed to change the actuating voltage Va applied to the electrode 46a of the liquid displaying device 46. Therefore, the brightness of the liquid displaying device 46 can be controlled by changing the voltage Vs of the picture signal Sp, so that an excellent display characteristic in gray scale can be obtained in the matrix displaying apparatus.
3. Problems to be Solved by the Invention
However, in the conventional matrix type liquid crystal displaying apparatus 31 disclosed as the invention in patent gazette No. H3-34077 (1991), because the liquid crystal displaying device 16 is actuated by applying the alternating current exciting voltage superimposed on the scanning signal or a zero voltage to the liquid crystal displaying device 16 through the gate signal line 12 and the second MOS-FET 14, a display characteristic in gray scale is not obtained in the conventional matrix type liquid crystal displaying apparatus 31 disclosed in the patent gazette No. H3-34077 (1991) as the invention.
Also, in the matrix displaying apparatus disclosed as prior art in the aforementioned patent gazette No. H3-34077 (1991), a polarity of the voltage Vs of the picture signal Sp applied to the drain D of the first MOS-FET 44 is inverted every field period (1/60 second) or every frame period (1/30 second) to invert a polarity of the actuating voltage Va applied to the liquid crystal displaying device 46 every field period or every frame period for the purpose of actuating the liquid crystal displaying device 46. In this case, the actuating voltage Va is applied to the liquid crystal displaying device 46 at a low frequency such as 30 Hz. Therefore, in cases where a voltage maintaining characteristic in a liquid crystal layer of the liquid crystal displaying device 46 is not sufficient, the actuating voltage Va applied to the liquid crystal displaying device 46 is decreased, so that there is a drawback that a luminance (or brightness) of an image displayed by the matrix displaying apparatus is lowered or a flicker occurs in the image.